课程说明及重点
高压制程电子产品一般最大的可靠性问题是静电放电(ESD) 很差、闩锁(LU)能力也很差，而且模拟高压电路输出端口又会占很大面积，这会影响使其ESD能力通常非常不佳。ESD)/LU破坏是影响IC可靠性的重要因素也是延缓产品上市的主因，因此无论由制程上、设计上全方位的防护措施是必要的。本课程是高压集成IC
ESD/LU防护设计上之实务课程，更是各高压集成IC产品ESD可靠度防护上最热门的技术。
本课程将从各种HV CMOS元器件、晶圆厂技术平台、HV组件的汲极工程、高压元器件ESD/LU能力如何测试介绍起，进而谈论HV
CMOS 的各电性、可靠度缺点、晶圆厂HV ESD/LU 防护设计法则及各种ESD/LU保护策略及如何保护HV
LDMOS与HV 集成电路ESD/LU防护实际案例分析，最后期许学员能对HV制程工艺及组件结构充分理解，并熟悉HV
IC静电防护及LU免疫设计之防制意义。
授课对象
现职从事模拟IC与电子产品之RD设计、布局、制造、产品应用与品管、品保、FA相关技术人员 (对ESD/LU防护已有认识者)。
课程大纲
第一阶段 :
I. High-Voltage CMOS Devices
◎ What’s an HV Technology ?
◎ How These Products Use the HV Process ?
◎ Foundry Technology Platform
II. Device Engineering for HV Devices
◎ Basic Concepts of an HV IC
◎ Well Engineerings
◎ Electrical Behaviors
III. HV ESD/LU Testing Issues
◎ How to Do an HV IC ESD Testing ?
◎ How to Do an HV IC Latch-up Testing ?
第二阶段:
III. Weakness Issues in the HV CMOS Process
◎ High Resistive ESD Element Influence
◎ Intrinsic HV nMOS Reliability Problem
◎ Why ESD Level of the HV-CMOS I/O Protection Circuit
is So Bad ?
◎ How About the Occurred Failure Mode in the HV
CMOS ?
◎ HV Multi-Finger O/P nMOS Driver Protection Challenge
◎ Impact of Low-Holding-Voltage Issue in HV CMOS
Technology
IV HV ESD/LU Rules (ex: 5V/30V/40V)
◎ Foundry HV ESD Design Rules
◎ Foundry HV LU Design Rules
V. Some Strategies of ESD/LU Protection Design in
a HV CMOS Process
◎ How to Improve Low Vh ?
◎ How to Adjust Vt1 ?
◎ How to Guarantee That Vt2 >Vt1 ?
◎ How About the Single Finger Width Effect ?
◎ Which One Device Is More Better ?
◎ How About the N-Well Effect in a HV Drain Side
?
Day 3:
VI. How to Protect the HV LDMOS?
◎How to Do a Good ESD Immunity in the HV LDMOS?
◎ESD Protection Methods & Patents for the HV
LDMOS
VII. (HV ESD/LU Cases Study)
VIII. Summary
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