Overview
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This two-day workshop covers, via lecture and lab, the basics of formal verification. On the first day, students will apply a formal verification flow for:
- Verifying a design
- Debugging a failed design
On the second day, students will apply an extended flow in order to:
- Optimize Formality for common hardware design transformations
- Increase debugging capability through techniques such as pattern analysis
- Maximize verification performance
Objectives
At the end of this workshop the student should be able to:
- Describe where Formality fits in the design flow
- Read a reference design and the libraries for that design into Formality
- Read a revised design and the libraries for that design into Formality
- Set up for verification interactively and with scripts
- Handle common design transformations for easiest verification
- Guide Formality in matching names between two designs
- Verify that two designs are equivalent
- Debug designs proven not to be equivalent
- Optimize reads, compare point matching and verification
Audience Profile
Design or Verification engineers who understand traditional functional verification methods, and who want to perform verification more quickly, without using vectors.
Prerequisites
Knowledge of digital logic.
Course Outline
1.
- Introduction
- Controlling Formality
- Setting up and running Formality
- Debugging designs proved not equivalent
2.
- Design transformations and their effect on equivalence checking
- Advanced debugging
- Maximizing performance
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