1、培训过程中，如有部分内容理解不透或消化不好，可免费在以后培训班中重听；
        2、培训结束后,培训老师留给学员手机和Email,免费提供半年的技术支持，充分保证培训后出效果；
        3、培训合格学员可享受免费推荐就业机会。 ☆合格学员免费颁发相关工程师等资格证书，提升您的职业资质。专注高端培训13年，曙海提供的证书得到本行业的广泛认可，学员的能力得到大家的认同，受到用人单位的广泛赞誉。

培训方式以讲课和实验穿插进行。

This course teaches the key features and benefits of the SystemVerilog testbench language and its use in VCS. This course will provide the skills required to write an object-oriented SystemVerilog testbench and verify a device under test with coverage-driven random stimulus.

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Concepts covered during the course include developing an interface between the SystemVerilog test program and the Device Under Test (DUT), random stimulus generation, language syntax, coding style recommendations, object oriented programming concepts, functional coverage and verification methodology (VMM) introduction.

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During lab exercises the student will get practical experience in writing and debugging SystemVerilog testbench code using VCS and testbench debugger (DVE).By the end of this workshop you should be able to:

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●Simulate Verilog designs using VCS
●Debug Verilog designs using VCS
●Run fast RTL-level regression tests for your Verilog design
●Run fast gate-level regression tests for your Verilog design
●Acquire the skills and knowledge to successfully implement coverage driven verification methodology using Synopsys tools

?Unit1

1, VCS Simulation Basics

2, VCS Debugging Basics

3,Debuggin with DVE

4,PostProcessing with VCD + Files

Unit 2

5, Debugging Simulation Mismatches

6, Fast RTL Level Verification

7, Fast Gate level verification

8,Code Coverage