嵌入式培训
嵌入式Linux就业班马上开课了 详情点击这儿
上 海 :021-51875830
北 京 :010-51292078
南 京 :025-68662821
武 汉 :027-50767718
成 都 :4008699035

深 圳 :4008699035

沈 阳: 024-31298103
郑 州: 0371-63710058
石 家 庄: 4008699035
广 州: 020-61137349
西 安: 029-86699670
免费报名电话
Training in English

曙海研发与生产网址:www.shanghai66.cn
     
  首 页   手机浏览模式  课 程 介 绍    培 训 报 名   企业培训   付款方式    讲师介绍    学员评价    关于我们   联系我们   承接项目
嵌入式协处理器--FPGA
FPGA项目实战系列课程----
嵌入式OS--3G手机操作系统
嵌入式协处理器--DSP
手机/网络/动漫游戏开发
嵌入式OS-Linux
嵌入式CPU--ARM
嵌入式OS--WinCE
单片机培训
嵌入式硬件设计
Altium Designer Layout高速硬件设计
嵌入式OS--VxWorks
PowerPC嵌入式系统/编译器优化
PLC编程/变频器/数控/人机界面 
开发语言/数据库/软硬件测试
3G手机软件测试、硬件测试
芯片设计/大规模集成电路VLSI
云计算、物联网
开源操作系统Tiny OS开发
小型机系统管理
其他类
WEB在线客服
南京WEB在线客服
武汉WEB在线客服
西安在线客服
广州WEB在线客服
沈阳在线客服
郑州在线客服
石家庄在线客服
点击这里给我发消息  
QQ客服一
点击这里给我发消息  
QQ客服二
点击这里给我发消息
QQ客服三
  双休日、节假日及晚上可致电值班电话:4008699035 值班手机:15921673576 或加qq:1299983702和微信:shuhaipeixun

值班QQ:
点击这里给我发消息

值班网页在线客服,点击交谈:
 
网页在线客服

 
公益培训通知与资料下载
企业招聘与人才推荐(免费)

合作企业最新人才需求公告

◆招人、应聘、人才合作,
请把需求发到officeoffice@126.com或
访问曙海旗下网站---
电子人才网
www.morning-sea.com.cn
合作伙伴与授权机构
现代化的多媒体教室
曙海招聘启示
曙海动态
 
  Functional verification培训
   入学要求

        学员学习本课程应具备下列基础知识:
        ◆ 电路系统的基本概念。

   班级规模及环境
       为了保证培训效果,增加互动环节,我们坚持小班授课,每期报名人数限3到5人,多余人员安排到下一期进行。
   上课时间和地点
上课地点:【上海】:同济大学(沪西)/新城金郡商务楼(11号线白银路站) 【深圳分部】:电影大厦(地铁一号线大剧院站)/深圳大学成教院 【北京分部】:北京中山学院/福鑫大楼 【南京分部】:金港大厦(和燕路) 【武汉分部】:佳源大厦(高新二路) 【成都分部】:领馆区1号(中和大道) 【沈阳分部】:沈阳理工大学/六宅臻品 【郑州分部】:郑州大学/锦华大厦 【石家庄分部】:河北科技大学/瑞景大厦
最近开课时间(周末班/连续班/晚班)
Functional verification培训:2024年1月8日
   学时
     ◆课时: 共5天,30学时

        ◆外地学员:代理安排食宿(需提前预定)
        ☆注重质量
        ☆边讲边练

        ☆合格学员免费推荐工作

        ☆合格学员免费颁发相关工程师等资格证书,提升您的职业资质

        专注高端培训15年,曙海提供的证书得到本行业的广泛认可,学员的能力
        得到大家的认同,受到用人单位的广泛赞誉。

        ★实验设备请点击这儿查看★
   最新优惠
       ◆团体报名优惠措施:两人95折优惠,三人或三人以上9折优惠 。注意:在读学生凭学生证,即使一个人也优惠500元。
   质量保障

        1、培训过程中,如有部分内容理解不透或消化不好,可免费在以后培训班中重听;
        2、培训结束后,培训老师留给学员手机和Email,免费提供半年的技术支持,充分保证培训后出效果;
        3、培训合格学员可享受免费推荐就业机会。 ☆合格学员免费颁发相关工程师等资格证书,提升您的职业资质。专注高端培训13年,曙海提供的证书得到本行业的广泛认可,学员的能力得到大家的认同,受到用人单位的广泛赞誉。

  Functional verification培训


第一阶段 Incisive Comprehensive Coverage

Course Description

This is an Engineer Explorer series course. The Engineer Explorer courses explore advanced topics.

This course explores Incisive? comprehensive coverage features, with which you can measure how thoroughly your testbench exercises your design. The course addresses coverage of SystemC, VHDL, Verilog?, and mixed-language designs. Not all coverage features are available with all languages.

The course discusses the collection and analysis of the following types of coverage:

  • Code (block, expression, toggle, state, and arc) coverage
  • Data-oriented functional coverage using SystemVerilog covergroups
  • Control-oriented functional coverage using PSL and SystemVerilog assertions

Learning Objectives

After completing this course you will be able to:

  • Effectively use the Incisive comprehensive coverage with your SystemC, VHDL, Verilog, and mixed-language designs
第二阶段 Incisive SystemC, VHDL, and Verilog Simulation

Course Description

This course addresses Incisive? mixed-language (SystemC?, VHDL, and Verilog?) event-driven digital simulation. The course takes you through the compilation, elaboration, simulation, and interactive debug process, at each step explaining the most commonly used options. This course treats the SystemC, VHDL, and Verilog languages equivalently. You can do the labs in your choice of language.

Learning Objectives

After completing this course you will be able to:

  • Compile, elaborate, link, and simulate a design: Understand how to specify the inputs and outputs at each phase, configure the design, and control each process for effectiveness and optimal performance.
  • Debug a design with the textual interactive simulation interface: Briefly examine most of the interactive commands for the purpose of understanding what capabilities are available and how you can use them in a script to drive batched regression tests; practice these capabilities in the context of a scripted debug scenario.
  • Debug a design with the graphical interactive simulation interface: Examine many of the capabilities of the feature-rich SimVision graphical simulation analysis environment; practice these capabilities in the context of a scripted debug scenario.
  • Utilize some of the other tools available to assist your simulation-related efforts to: Verify your platform's patch level, protect your intellectual property, “lint” your design and filter and sort the analysis report, manage your library of compiled design objects, compare simulation traces, package your design for transmittal, and much more.
  • Optionally: Understand the issues involved with mixed-language instantiation, simulation, and debugging; examine the mechanics of interconnecting components of multiple languages; choose and simulate a mixed-language design configuration containing at least one HDL component and at least one SystemC component.
 

节假日、双休日及晚上请垂询招生热线 :4008699035


备 案 号 : 沪 IC P备 08026168 号

.(2014年7月11).......................................................................................................