嵌入式培训
嵌入式Linux就业班马上开课了 详情点击这儿
上 海 :021-51875830
北 京 :010-51292078
南 京 :025-68662821
武 汉 :027-50767718
成 都 :4008699035

深 圳 :4008699035

沈 阳: 024-31298103
郑 州: 0371-63710058
石 家 庄: 4008699035
广 州: 020-61137349
西 安: 029-86699670
免费报名电话
Training in English

曙海研发与生产网址:www.shanghai66.cn
     
  首 页   手机浏览模式  课 程 介 绍    培 训 报 名   企业培训   付款方式    讲师介绍    学员评价    关于我们   联系我们   承接项目
嵌入式协处理器--FPGA
FPGA项目实战系列课程----
嵌入式OS--3G手机操作系统
嵌入式协处理器--DSP
手机/网络/动漫游戏开发
嵌入式OS-Linux
嵌入式CPU--ARM
嵌入式OS--WinCE
单片机培训
嵌入式硬件设计
Altium Designer Layout高速硬件设计
嵌入式OS--VxWorks
PowerPC嵌入式系统/编译器优化
PLC编程/变频器/数控/人机界面 
开发语言/数据库/软硬件测试
3G手机软件测试、硬件测试
芯片设计/大规模集成电路VLSI
云计算、物联网
开源操作系统Tiny OS开发
小型机系统管理
其他类
WEB在线客服
南京WEB在线客服
武汉WEB在线客服
西安WEB在线客服
广州WEB在线客服
点击这里给我发消息  
QQ客服一
点击这里给我发消息  
QQ客服二
点击这里给我发消息
QQ客服三
公益培训通知与资料下载
企业招聘与人才推荐(免费)

合作企业最新人才需求公告

◆招人、应聘、人才合作,
请把需求发到officeoffice@126.com或
访问曙海旗下网站---
电子人才网
www.morning-sea.com.cn
合作伙伴与授权机构
现代化的多媒体教室
曙海招聘启示
曙海动态
 
  Physical Design Implementation培训课程
   班级规模及环境
       为了保证培训效果,增加互动环节,我们坚持小班授课,每期报名人数限3到5人,多余人员安排到下一期进行。
   上课时间和地点
上课地点:【上海】:同济大学(沪西)/新城金郡商务楼(11号线白银路站) 【深圳分部】:电影大厦(地铁一号线大剧院站)/深圳大学成教院 【北京分部】:北京中山学院/福鑫大楼 【南京分部】:金港大厦(和燕路) 【武汉分部】:佳源大厦(高新二路) 【成都分部】:领馆区1号(中和大道) 【沈阳分部】:沈阳理工大学/六宅臻品 【郑州分部】:郑州大学/锦华大厦 【石家庄分部】:河北科技大学/瑞景大厦
最近开课时间(周末班/连续班/晚班)
Design Implementation培训课程:2024年1月8日
   学时
     ◆课时: 共5天,30学时

        ◆外地学员:代理安排食宿(需提前预定)
        ☆注重质量
        ☆边讲边练

        ☆合格学员免费推荐工作

        ☆合格学员免费颁发相关工程师等资格证书,提升您的职业资质

        专注高端培训15年,曙海提供的证书得到本行业的广泛认可,学员的能力
        得到大家的认同,受到用人单位的广泛赞誉。

        ★实验设备请点击这儿查看★
   最新优惠
       ◆团体报名优惠措施:两人95折优惠,三人或三人以上9折优惠 。注意:在读学生凭学生证,即使一个人也优惠500元。
   质量保障

        1、培训过程中,如有部分内容理解不透或消化不好,可免费在以后培训班中重听;
        2、培训结束后,培训老师留给学员手机和Email,免费提供半年的技术支持,充分保证培训后出效果;
        3、培训合格学员可享受免费推荐就业机会。 ☆合格学员免费颁发相关工程师等资格证书,提升您的职业资质。专注高端培训13年,曙海提供的证书得到本行业的广泛认可,学员的能力得到大家的认同,受到用人单位的广泛赞誉。

  Physical Design Implementation培训课程
培训方式以讲课和实验穿插进行

课程描述:

第一阶段 IC Compiler 1

Overview
The workshop is based on Synopsys? Lynx Compatible Reference Methodology (LCRM) flow:

  • The CMM Data Setup unit covers how to load the files and libraries required by IC Compiler, as well as setting up scenarios for multi-corner multi-mode (MCMM) analysis and optimization.
  • The Design Planning unit covers how to create a block-level floorplan, including macro placement and a power network, which results in acceptable routeability and timing throughout the flow.
  • The Placement unit focuses on optimizing the placement and logic for timing, congestion, leakage power, and scan-chain ordering.
  • The lock Tree Synthesis (CTS) unit covers controlling and building clock trees, optimizing clock power dissipation, and performing additional timing optimization.
  • The outing unit covers routing of the clock nets, followed by signal routing and optimization, including redundant via insertion, antenna fixing, and crosstalk reduction.
  • The Design for Manufacturability unit covers steps to improve yield and reliability, including wire spreading/widening, diode insertion, inserting filler cells, redundant via insertion, and signoff metal filling using IC Validator. The unit concludes by covering how to generate design data for final verification and validation, as well as converting the block into a hard macro for top-level integration.

Every lecture is accompanied by a comprehensive hands-on lab. Labs use the LCRM directory structure and scripts.

Objectives
At the end of this workshop you should be able to use IC Compiler to:
  • Use the GUI to analyze the layout during the various design phases
  • Perform and debug data setup to create an initial design cell which is ready for design planning and placement; This includes loading required files and libraries, creating a Milkyway design library, and applying common timing and optimization controls
  • Create scenarios for MCMM timing, leakage power, and CTS optimization
  • Create a non-hierarchical block-level floorplan for always-on single-voltage (non-UPF) designs that will be routable and will achieve timing closure
  • Perform standard cell placement and related optimizations to minimize timing violations, congestion, and leakage power; Insert spare cells
  • Analyze congestion maps and timing reports
  • Apply any required CTS constraints, targets, and controls
  • Perform pre-CTS power optimization to reduce clock tree power
  • Execute the recommend clock tree synthesis and optimization flow
  • Analyze clock tree and timing results post-CTS
  • Perform routing setup to control DRC fixing, delay calculation, redundant via insertion, antenna fixing, and crosstalk reduction
  • Route the clock nets
  • Route the signal nets and perform post-route optimization
  • Analyze and fix physical DRC and LVS violations
  • Perform functional ECOs
  • Perform design for manufacturability steps
  • Generate output files required for final validation/verification

Course Outline

Unit 1
  • Introduction
  • MCMM Data Setup
  • Design Planning
Unit 2
  • Design Planning (Lab continued)
  • Placement
  • Clock Tree Synthesis
Unit 3
  • Clock Tree Synthesis (Lab continued)
  • Routing
  • Design for Manufacturability
  • Customer Support

第二阶段 IC Compiler 2: Hierarchical Design Planning

Overview
The workshop teaches floorplan preparation for large and complex integrated circuits. You will learn to partition a design into hierarchical sub-blocks for implementation in IC Compiler. All the floorplan, constraint, and timing information required for implementation is created.

We begin with an initialized floorplan (learned in the IC Compiler 1 workshop). Next, standard cell and macro placement, using plan groups, guide the development of a physical hierarchy. Manipulation of the physical hierarchy is discussed in detail.

We then demonstrate a number of methods for improving the quality of the floorplan including: power network synthesis, in-place optimization, and budgeting. Finally, we create soft macro blocks suitable for place and route processing.

Hands-on labs for all course units use a hierarchical design allowing exploration of all aspects of virtual flat floorplanning.

Objectives
At the end of this workshop the student should be able to:
  • Describe the IC Compiler Design Planning Virtual Flat Placement flow
  • Manipulate the hierarchy and create plan groups using the Hierarchy Browser
  • Perform Power Planning using IC Compiler's Power Network analysis and synthesis capabilities
  • Describe the IC Compiler Design Planning Virtual Flat Placement flow
  • Manipulate the hierarchy and create plan groups using the Hierarchy Browser
  • Perform power planning using IC Compiler's power network analysis and synthesis capabilities
  • Execute virtual flat placement and refine the plan groups
  • Perform in-place optimization
  • Perform plan-group-aware routing (PGAR) pin assignment on all blocks
  • Perform design budgeting and generate block-level SDC files
  • Generate ILM models for chip-level timing analysis and budgeting
  • Define and develop effective time budgeting for place & route in IC Compiler

Course Outline

 
  • Introduction & Overview
  • Partition Top Level into Plan Groups
  • Create Block Macros and Integrate Top
 

节假日、双休日及晚上请垂询招生热线 :4008699035


备 案 号 : 沪 IC P备 08026168 号

.(2014年7月11).......................................................................................................